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| MC74HC4060A 14-Stage Binary Ripple Counter With Oscillator High-Performance Silicon-Gate CMOS The MC74C4060A is identical in pinout to the standard CMOS MC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 14 master-slave flip-flops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flip-flop feeds the next and the frequency at each output is half of that of the preceding one. The state of the counter advances on the negative-going edge of the Osc In. The active-high Reset is asynchronous and disables the oscillator to allow very low power consumption during stand-by operation. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with Osc Out 2 of the HC4060A. http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP-16 N SUFFIX CASE 648 MC74HC4060AN AWLYYWW 1 16 16 1 SO-16 D SUFFIX CASE 751B 1 HC4060A AWLYWW 16 * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 390 FETs or 97.5 Equivalent Gates Pinout: 16-Lead Plastic Package (Top View) VCC 16 Q10 15 Q8 14 Q9 13 Osc Osc Reset Osc In Out 1 Out 2 12 11 10 9 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week HC40 60A ALYW LOGIC DIAGRAM Osc Out 1 Osc Out 2 10 9 7 5 4 6 14 13 15 1 2 3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 Osc In 11 1 Q12 2 Q13 3 Q14 4 Q6 5 Q5 6 Q7 7 Q4 8 GND Reset 12 FUNCTION TABLE Clock Reset L L H Output State No Charge Advance to Next State All Outputs Are Low Pin 16 = VCC Pin 8 = GND ORDERING INFORMATION Device MC74HC4060AN MC74HC4060AD MC74HC4060ADR2 MC74HC4060ADT MC74HC4060ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel X (c) Semiconductor Components Industries, LLC, 2000 1 March, 2000 - Rev. 2 Publication Order Number: MC74HC4060A/D MC74HC4060A IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range - 65 to + 150 260 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS IIII I I I I IIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII II I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I Symbol VCC Parameter Min Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) 2.5* 0 Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V *The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at 2.0 V by driving Pin 11 with an external clock source. DC CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH Parameter Minimum High-Level Input Voltage Condition Vout = 0.1V or VCC -0.1V |Iout| 20A VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.48 3.98 5.48 85C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.34 3.84 5.34 125C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.20 3.70 5.20 Unit V VIL Maximum Low-Level Input Voltage Vout = 0.1V or VCC - 0.1V |Iout| 20A V VOH Minimum High-Level Output Voltage (Q4-Q10, Q12-Q14) Vin = VIH or VIL |Iout| 20A Vin =VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA V 3.0 4.5 6.0 http://onsemi.com 2 MC74HC4060A DC CHARACTERISTICS (Voltages Referenced to GND) Symbol VOL Parameter Maximum Low-Level Output Voltage (Q4-Q10, Q12-Q14) Condition Vin = VIH or VIL |Iout| 20A Vin = VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA VCC V 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| 0.7mA |Iout| 1.0mA |Iout| 1.3mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| 0.7mA |Iout| 1.0mA |Iout| 1.3mA 3.0 4.5 6.0 6.0 6.0 Guaranteed Limit -55 to 25C 0.1 0.1 0.1 0.26 0.26 0.26 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.1 4 85C 0.1 0.1 0.1 0.33 0.33 0.33 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.0 40 125C 0.1 0.1 0.1 0.40 0.40 0.40 1.9 4.4 5.9 2.20 3.70 5.20 0.1 0.1 0.1 0.40 0.40 0.40 1.0 160 A A V V Unit V VOH Minimum High-Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| 20A Vin =VCC or GND VOL Maximum Low-Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| 20A Vin =VCC or GND Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 6.0 10 30 50 300 180 60 51 500 350 250 200 195 75 39 33 75 60 15 13 85C 9.0 14 28 45 375 200 75 64 750 450 275 220 245 100 49 42 95 75 19 16 125C 8.0 12 25 40 450 250 90 75 1000 600 300 250 300 125 61 53 125 95 24 20 Unit MHz tPLH, tPHL Maximum Propagation Delay, Osc In to Q4* (Figures 1 and 4) ns tPLH, tPHL Maximum Propagation Delay, Osc In to Q14* (Figures 1 and 4) ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) ns tPLH, tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4) ns http://onsemi.com 3 MC74HC4060A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) - continued Symbol tTLH, tTHL Parameter Maximum Output Transition Time, Any Output (Figures 1 and 4) VCC V 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 75 27 15 13 10 85C 95 32 19 16 10 125C 110 36 22 19 10 Unit ns Cin Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). * For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [93.7 + 59.3 (n-1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n-1)] ns VCC = 3.0 V: tP = [61.5+ 34.4 (n-1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n-1)] ns Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 35 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol trec Parameter Minimum Recovery Time, Reset Inactive to Clock (Figure 2) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 100 75 20 17 75 27 15 13 75 27 15 13 1000 800 500 400 85C 125 100 25 21 95 32 19 16 95 32 19 16 1000 800 500 400 125C 150 120 30 25 110 36 23 19 110 36 23 19 1000 800 500 400 Unit ns tw Minimum Pulse Width, Clock (Figure 1) ns tw Minimum Pulse Width, Reset (Figure 2) ns tr, tf Maximum Input Rise and Fall Times (Figure 1) ns NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC4060A PIN DESCRIPTIONS INPUTS Osc In (Pin 11) Osc Out 1, Osc Out 2 (Pins 9, 10) Negative-edge triggering clock input. A high-to-low transition on this input advances the state of the counter. Osc In may be driven by an external clock source. Reset (Pin 12) Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state (forcing all Q outputs low) and disables the oscillator. OUTPUTS Q4--Q10, Q12-Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3) Oscillator outputs. These pins are used in conjunction with Osc In and the external components to form an oscillator. When Osc In is being driven with an external clock source, Osc Out 1 and Osc Out 2 must be left open circuited. With the crystal oscillator configuration in Figure 6, Osc Out 2 must be left open circuited. Active-high outputs. Each Qn output divides the Clock input frequency by 2N. The user should note the Q1, Q2, Q3 and Q11 are not available as outputs. SWITCHING WAVEFORMS tw VCC GND 1/fMAX tPLH Q 90% 50% 10% tTLH tTHL tPHL Q Reset tPHL 50% trec Osc In 50% GND 50% GND tw tf Osc In 90% 50% 10% tr VCC VCC Figure 1. Figure 2. TEST POINT VCC Qn 50% GND tPLH Qn+1 50% tPHL DEVICE UNDER TEST OUTPUT CL* *Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit http://onsemi.com 5 MC74HC4060A Q4 7 Q5 5 Q12 1 Q13 2 Q14 3 C Q C Q C Q C Q C Q C Q C R Osc Out 2 9 Q C R Q C Q C Q C Q C Osc Out 1 10 Q6 = Pin 4 Q7 = Pin 6 Q8 = Pin 14 Q9 = Pin 13 Q10 = Pin 15 VCC = Pin 16 GND = Pin 8 Osc In Reset 11 12 Figure 5. Expanded Logic Diagram Reset 12 For 2.0V VCC 6.0V 10Rtc > RS > 2Rtc 400Hz f 400Khz: Osc In 11 Osc Out 1 RS 10 Rtc Ctc Osc Out 2 9 f [ 3 R1 Ctc (f in Hz, Rtc in ohms, Ctc in farads) tc The formula may vary for other frequencies. Figure 6. Oscillator Circuit Using RC Configuration Reset 12 Osc In 11 Rf Osc Out 1 10 9 Osc Out 2 R1 C1 C2 Figure 7. Pierce Crystal Oscillator Circuit http://onsemi.com 6 MC74HC4060A TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25C; Input = Pin 11, Output = Pin 10) Type Input Resistance, Rin Output Impedance, Zout (4.5V Supply) Input Capacitance, Cin Output Capacitance, Cout Series Capacitance, Ca Open Loop Voltage Gain with Output at Full Swing, 3Vdc Supply 4Vdc Supply 5Vdc Supply 6Vdc Supply 60M Minimum 200 (See Text) 5pF Typical 7pF Typical 5pF Typical 5.0 Expected Minimum 4.0 Expected Minimum 3.3 Expected Minimum 3.1 Expected Minimum Positive Reactance (Pierce) PIERCE CRYSTAL OSCILLATOR DESIGN RS 1 2 1 CO LS CS 2 1 Re Xe 2 Value are supplied by crystal manufacturer (parallel resonant crystal). Figure 8. Equivalent Crystal Networks RS -jXCo Zload -jXCs -jXC2 R Rload Ca Xload jXLs -jXC Cin Cout NOTE: C = C1 + Cin and R = R1 + Rout. Co is considered as part of the load. Ca and Rf typically have minimal effect below 2MHz. Values are listed in Table 1. Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier http://onsemi.com 7 MC74HC4060A DESIGN PROCEDURES The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180C. Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation. Ze * jX (Rs ) jXL jXCs + * jXCCo) Rs ) jXsL** jXC) + Re ) jXe o s s Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency. The maximum Rs for the crystal should be used in the equation. Step 2: Determine , the attenuation, of the feedback network. For a closed-loop gain of 2,A = 2, = 2/A where A is the gain of the HC4060A amplifier. Step 3: Determine the manufacturer's loading capacitance. For example: A manufacturer may specify an external load capacitance of 32pF at the required frequency. Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of 100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2foLS/Q) - Rs where Ls and Rs are crystal parameters. Step 5: Simultaneously solve, using a computer, b X@ + R @ Re )C C2XC2e * XC) X (X (with feedback phase shift = 180) ( Eq 1 ) X + XC2 ) XC ) ReRC2 + XCload (where the loading capacitor is an external load, not including Co) RXCoXC2 [(XC ) XC2)(XC ) XCo) * XC(XC ) XCo ) XC2)] Rload + X2C2(XC ) XCo)2 ) R2(XC ) XCo ) XC2)2 Xe ( Eq 2 ) ( Eq 3 ) Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin. Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that Q = 2foLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure. CHOOSING R1 the first overtone. Rf must be large enough so as to not affect Power is dissipated in the effective series resistance of the the phase of the feedback network in an appreciable manner. crystal. The drive level specified by the crystal manufacturer ACKNOWLEDGEMENTS AND RECOMMENDED is the maximum stress that a crystal can withstand without REFERENCES damage or excessive shift in frequency. R1 limits the drive The following publications were used in preparing this level. data sheet and are hereby acknowledged and recommended To verify that the maximum dc supply voltage does not for reading: overdrive the crystal, monitor the output frequency as a Technical Note TN-24, Statek Corp. function of voltage at Osc Out 2 (Pin 9). The frequency Technical Note TN-7, Statek Corp. should increase very slightly as the dc supply voltage is D. Babin, "Designing Crystal Oscillators", Machine increased. An overdriven crystal will decrease in frequency Design, March 7, 1985. or become unstable with an increase in supply voltage. The D. Babin, "Guidelines for Crystal Oscillator Design", operating supply voltage must be reduced or R1 must be Machine Design, April 25, 1985. increased in value if the overdriven condition exists. The ALSO RECOMMENDED FOR READING: user should note that the oscillator start-up time is E. Hafner, "The Piezoelectric Crystal Unit-Definitions proportional to the value of R1. and Method of Measurement", Proc. IEEE, Vol. 57, No. 2, SELECTING Rf Feb., 1969. The feedback resistor, Rf, typically ranges up to 20M. Rf D. Kemper, L. Rosine, "Quartz Crystals for Frequency determines the gain and bandwidth of the amplifier. Proper Control", Electro-Technology, June, 1969. bandwidth insures oscillation at the correct frequency plus P. J. Ottowitz, "A Guide to Crystal Selection", Electronic roll-off to minimize gain at undesirable frequencies, such as Design, May, 1966. http://onsemi.com 8 MC74HC4060A 1 Clock Reset Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q12 Q13 Q14 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 Figure 11. Timing Diagram http://onsemi.com 9 MC74HC4060A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S http://onsemi.com 10 MC74HC4060A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.25 (0.010) 0.15 (0.006) T U S A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E http://onsemi.com 11 EEE CCC EEE CCC M -W- DIM A B C D F G H J J1 K K1 L M MC74HC4060A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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